Incorporating trigger loads in branch histories for branch...

Details Incorporating trigger loads in branch histories for branch... Incorporating trigger loads in branch histories for branch...

2000-12-15

2004-08-17

Chan, Eddie (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Branching

C712S219000

Reexamination Certificate

active

06779108

ABSTRACT:

FIELD OF THE INVENTION
This invention pertains to branch predictions in a computer, and more particularly to branch predictions based on load instructions.
BACKGROUND OF THE INVENTION
In an effort to improve processor efficiency, computers today engage in branch prediction. Branch prediction involves speculating as to which way a program will go when it reaches a branch point. For example,
FIG. 1
shows program
105
with branch instruction
110
. At the branch, the program will proceed either with instruction
115
-
1
or instruction
115
-
2
, depending on whether or not the branch is taken. The processor attempts to determine which path will be followed: i.e., whether instruction
115
-
1
or instruction
115
-
2
will follow instruction
110
. When successful, branch prediction enables processors, especially pipeline processors (which execute several instructions at different stages at the same time), to execute programs more quickly.
But when a branch prediction fails, any instructions executed by the processor on the wrong path have been wasted. The processor loses any advantage provided by the branch predictor, and needs to execute the instructions along the correct path.
Frequently, the branch taken after a branch instruction correlates well with data recently loaded from memory. For example, in
FIG. 1
, instruction
120
may be a load instruction, on whose value branch instruction
110
depends. But currently, branch prediction is based on factors such as the path leading to the branch, previous occurrences of the branch, and the values of operands of the branch instruction. Branch prediction, so far, does not correlate with the value of data loaded from memory.
The present invention addresses this and other problems associated with the prior art.


REFERENCES:
patent: 3577189 (1971-05-01), Cocke
patent: 5884059 (1999-03-01), Favor et al.
patent: 6272623 (2001-08-01), Talcott
patent: 6367076 (2002-04-01), Imai et al.
patent: 6377942 (2002-04-01), Hinsley et al.
Srikanth T. Srinivasan and Alvin R. Lebeck, “Exploiting Load Latency Tolerance in Dynamically Scheduled Processors,” Feb. 13, 1998, pp. 1-18.
Timothy H. Heil, Zak Smith and J.E. Smith, “Improving Branch Predictors by Correlating on Data Values,” Nov. 1999, pp. 28-37.

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