Checkpoint table for selective instruction flushing in a specula

Circuit and method for initiating exception routines using...

Circuit and method for supporting misaligned accesses in the...

Circuit and method for tagging and invalidating...

Circuit arrangement and method of speculative instruction...

Circuit for controlling execution of loop in digital signal...

Circuit that implements semaphores in a multiprocessor...

Circuitry and method for performing branching without pipeline d

Circuits and methods for recovering link stack data upon...

Circuits, systems and methods for performing branch...

Circuits, systems, and methods for uniquely identifying a microp

Clock architecture for multi-processor systems

Combined branch prediction and cache prefetch in a microprocesso

Combining ALU and memory storage micro instructions by using an

Command execution controlling apparatus, command execution...

Common feature mode for microprocessors in a multiple...

Common-thread inter-process function calls invoked by jumps...

Communicating signals between semiconductor chips using...

Communication bus with hidden pre-fetch registers

Communication path to each part of distributed register file...