Clock architecture for multi-processor systems

Details Clock architecture for multi-processor systems Clock architecture for multi-processor systems

2007-04-11

2010-10-12

Chan, Eddie P (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

C713S400000

Reexamination Certificate

active

07814301

ABSTRACT:
In one embodiment, a computer system, comprises at least a first computing cell and a second computing cell, each computing cell comprising at least one processor, a routing device to couple the first and second computing cells, a global clock signal source coupled to the at least two computing cells to generate a global clock signal, at least one timing manager to generate a timing control signal, wherein the at least two computing cells comprise a local oscillator to generate a local clock signal, and a multiplexer coupled to receive the global clock signal, the local clock signal, and the timing control signal, and to output one of the global clock signal or the local clock signal in response to the control signal.

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