Electrical computers and digital processing systems: processing – Processing control – Processing sequence control
Patent
1997-03-19
1999-11-09
Ellis, Richard L.
Electrical computers and digital processing systems: processing
Processing control
Processing sequence control
G06F 928
Patent
active
059833440
ABSTRACT:
An apparatus and method for improving the execution speed of macro instructions which have an operand located in memory, and where the destination of the result is in memory. The apparatus includes an ALU Store which monitors micro instructions generated by a translator. When a macro instruction is fetched which has an operand located in memory, and the result is to be stored in the same location in memory, the translator generates a LOAD micro instruction followed immediately by an operation micro instruction which contains STORE indicia, such as a STORE suffix. The ALU Store latches the address created by the LOAD micro instruction, and uses this latched address in the following operation store micro instruction.
REFERENCES:
patent: 4090648 (1978-05-01), Asano et al.
patent: 4654786 (1987-03-01), Cochran et al.
patent: 5046040 (1991-09-01), Miyoshi
patent: 5317701 (1994-05-01), Reininger et al.
Hamacher et al., Computer Organization, Second Edition, McGraw-Hill Series in Computer Organization and Architecture, pp. 146-158, 1984.
Henry G. Glenn
Parks Terry
Ellis Richard L.
Huffman James W.
Integrated Device Technology Inc.
LandOfFree
Combining ALU and memory storage micro instructions by using an does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Combining ALU and memory storage micro instructions by using an , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Combining ALU and memory storage micro instructions by using an will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1470514