Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
1998-07-30
2001-04-24
Lee, Thomas (Department: 2182)
Electrical computers and digital processing systems: processing
Processing control
Branching
C712S223000, C712S241000
Reexamination Certificate
active
06223282
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of Korean Application No. 97-76387, filed Dec. 29, 1997, in the Korean Patent Office, the disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital signal processing chip, and more particularly, to a circuit for controlling execution of a loop in a digital signal processing chip which can prevent an error from being generated when the number of loop executions is zero, shorten the execution time upon realization of an entire algorithm, and reduce waste of a program memory.
2. Description of the Related Art
A digital signal processing chip is used a lot in fields necessary for a large amount of arithmetic calculation, i.e., an audio codec, echo canceling, etc. In the algorithms of these fields, many portions use a loop. Here, there is a case when a loop is executed a fixed number of times, but in many cases, the loop is repeated a variable number of times. Most of the digital signal processing chips input the number of loop executions to a control register, and then a designated section is repeated by the input number. Also, when a loop is repeated the variable number of times, a case when zero is input as the number of loop executions frequently occurs. At this time, an existing digital signal processing chip executes a loop once, and then the value of the control register is arbitrarily changed, thus generating an error. That is, the conventional digital signal processing chip generates an error when the number of loop executions is zero, i.e., when zero is input to the control register in which the number of loop executions is input. To be more specific, when the number of loop executions is zero, a loop is executed once, and then the control register has a maximum of its value, thus generating an error. In order to prevent the generation of the errors, the conventional digital signal processing chip always must perform a routine for checking whether the number of loop executions is zero in the case that the loop is repeated a variable number of times.
SUMMARY OF THE INVENTION
To solve the above and other problems, it is an object of the present invention to provide a circuit for controlling execution of a loop in a digital signal processing chip, which can prevent an error from being generated when the number of loop executions is zero, shorten the execution time when an entire algorithm is realized, and prevent waste of a program memory.
Additional objects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Accordingly, to achieve the above and other objects of the present invention, there is provided a circuit for controlling execution of a loop in a digital signal processing chip, including a least significant bit state detection unit to output an effective signal of a predetermined level according to the state of a least significant bit and the states of first and second signals, when every bit other than the least significant bit is zero as a result of detection of the state of each bit in a counter register to which the number of loop executions is loaded; a conditional clock output unit to receive a clock signal and the first and second signals and output the clock signal only when the first or second signal is effective; and an ending condition signal output unit to output the output signal of the least significant bit state detection unit when a signal output from the conditional clock output unit is effective.
It is preferable that the first signal is a loop ending signal which becomes effective when loop ending conditions are satisfied, and the second signal is a comparator loading signal which becomes effective when a final command address of the loop and an address for the command to be performed next are loaded to a loop comparator.
Preferably, the least significant bit state detection bit includes a plurality of PMOS gates connected to each other in series, wherein each gate is connected to the output ports of the remaining bits except for the least significant bit in the counter register, respectively; a first AND gate to perform an AND operation on the output of the output port of the least significant bit in the counter register and the comparator loading signal; a second AND gate to perform an AND operation on the output of the output port of the least significant bit in the counter register and the loop ending signal; an OR gate to perform an OR operation on the outputs of the first and second AND gates; and a PMOS gate connected to the plurality of PMOS gates in series, to receive the output of the OR gate and output the effective signal having a predetermined level.
It is preferable that the conditional clock output unit includes a first AND gate to perform an AND operation on the clock signal and the comparator loading signal; a second AND gate to perform an AND operation on the clock signal and the loop ending signal; and an OR gate to perform an OR operation on the outputs of the first and second AND gates.
Preferably, the ending condition signal output unit is an AND gate to perform an AND operation on the output signal of the conditional clock output unit and the output signal of the least significant bit state detection unit.
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Cao Chun
Lee Thomas
Samsung Electronics Co,. Ltd.
Staas & Halsey , LLP
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