Circuits, systems, and methods for uniquely identifying a microp

Clock architecture for multi-processor systems

Combined branch prediction and cache prefetch in a microprocesso

Combining ALU and memory storage micro instructions by using an

Command execution controlling apparatus, command execution...

Common feature mode for microprocessors in a multiple...

Common-thread inter-process function calls invoked by jumps...

Communicating signals between semiconductor chips using...

Communication bus with hidden pre-fetch registers

Communication path to each part of distributed register file...

Compare and branch mechanism

Compare branch instruction pairing within a single integer...

Compiling method of accessing a multi-dimensional array and syst

Compiling strong and weak branching behavior instruction blocks

Completion of asynchronous memory move in the presence of a...

Complex domain floating point VLIW DSP with data/program bus...

Complex vector executing clustered SIMD micro-architecture...

Component with a dynamically reconfigurable architecture

Compound instructions in a multi-threaded processor

Compressed instruction format for use in a VLIW processor