Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
Reexamination Certificate
2007-11-20
2007-11-20
Kim, Kenneth S. (Department: 2111)
Electrical computers and digital processing systems: processing
Processing control
Arithmetic operation instruction processing
C712S032000, C712S037000
Reexamination Certificate
active
11201842
ABSTRACT:
A programmable digital signal processor including a clustered SIMD microarchitecture includes a plurality of accelerator units, a processor core and a complex computing unit. Each of the accelerator units may be configured to perform one or more dedicated functions. The processor core includes an integer execution unit that may be configured to execute integer instructions. The complex computing unit may be configured to execute complex vector instructions. The complex computing unit may include a first and a second clustered execution pipeline. The first clustered execution pipeline may include one or more complex arithmetic logic unit datapaths configured to execute first complex vector instructions. The second clustered execution pipeline may include one or more complex multiplier accumulator datapaths configured to execute second complex vector instructions.
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Liu Dake
Nilsson Anders Henrik
Tell Eric Johan
Coresonic AB
Curran Stephen J.
Kim Kenneth S.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
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