Performance of a cache by including a tag that stores an...
Performance-based caching
Performing a memory write of a data unit without changing...
Performing a write cycle to memory in a multi-processor system
Performing direct cache access transactions based on a...
Performing overlapping burst memory accesses and interleaved mem
Performing useful computations while waiting for a line in a...
Peripheral device interface chip cache and data...
Physically-tagged cache with virtually-tagged fill buffers
Pin management of accelerator for interpretive environments
Pipelined cache memory deallocation and storeback
Pipelined digital signal processor and signal processing system
Pipelined flushing of a high level cache and invalidation of low
Pipelined instruction cache and branch prediction mechanism ther
Pipelined non-blocking level two cache system with inherent...
Pipelined snooping of multiple L1 cache lines
Pipelined snooping of multiple L1 cache lines
Pipelined stack caching circuit
Pipelined-systolic single-instruction stream multiple-data strea
Pipelining cache-coherence operations in a shared-memory...