Pipelined flushing of a high level cache and invalidation of low

Details Pipelined flushing of a high level cache and invalidation of low Pipelined flushing of a high level cache and invalidation of low

1996-10-07

1999-01-12

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711140, 711144, G06F 1300

Patent

active

058601007

ABSTRACT:
A L2 (high-level) cache according to the present invention implements an efficient pipelined algorithm for flushing the high-level cache and back-invalidating a L1 (low-level) cache. Initially, an address calculation stage calculates the address of a directory entry contained in an array of directory entries every clock cycle. Connected to this address calculation stage is a directory entry lookup stage. The directory entry lookup stage receives an address from the address calculation stage and retrieves the directory entry to be modified from the array of directory entries. Finally, a directory entry modification stage, connected to the directory entry lookup stage, receives the directory entry from the directory entry lookup stage. The directory entry modification stage first looks to see if the directory entry is not marked as invalid. If the directory entry is already marked as invalid, no further processing need be performed on the directory entry. If the directory entry modification stage determines the directory entry to not be invalid, the directory entry modification stage invalidates the directory entry to create a invalid directory entry. Next, the directory entry modification stage stores the invalid directory entry in the array of directory entries. The address calculation stage, the directory entry lookup stage, and the directory entry modification stage within the high-level cache can each perform a new operation every clock cycle. Also connected to the directory entry lookup stage is a castout stage. The castout stage receives a directory entry from the directory entry lookup stage and sends a flush signal to the processor. The flush signal directs the processor to invalidate a line in the low-level cache which corresponds to the directory entry. Also, the castout stage writes the modified contents of the high-level cache to memory.

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