Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2004-04-05
2008-11-11
Elmore, Stephen C (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S003000, C711S128000, C711S203000
Reexamination Certificate
active
07451271
ABSTRACT:
A virtually indexed, physically-tagged cache is combined with one or more virtually-tagged fill-buffers.
REFERENCES:
patent: 6006312 (1999-12-01), Kohn et al.
patent: 6009503 (1999-12-01), Liedtke
patent: 6539457 (2003-03-01), Mulla et al.
patent: 6557078 (2003-04-01), Mulla et al.
patent: 6976117 (2005-12-01), Clark et al.
Elmore Stephen C
Marvell International Ltd.
LandOfFree
Physically-tagged cache with virtually-tagged fill buffers does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Physically-tagged cache with virtually-tagged fill buffers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Physically-tagged cache with virtually-tagged fill buffers will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4050931