Pipelining cache-coherence operations in a shared-memory...

Details Pipelining cache-coherence operations in a shared-memory... Pipelining cache-coherence operations in a shared-memory...

2005-01-25

2005-01-25

Portka, Gary (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S140000, C711S141000

Reexamination Certificate

active

06848032

ABSTRACT:
One embodiment of the present invention provides a system that facilitates pipelining cache coherence operations in a shared memory multiprocessor system. During operation, the system receives a command to perform a memory operation from a processor in the shared memory multiprocessor system. This command is received at a bridge that is coupled to the local caches of the processors in the shared memory multiprocessor system. If the command is directed to a cache line that is subject to an in-progress pipelined cache coherency operation, the system delays the command until the in-progress pipelined cache coherency operation completes. Otherwise, the system reflects the command to local caches of other processors in the shared memory multiprocessor system. The system then accumulates snoop responses from the local caches of the other processor and sends the accumulated snoop response to the local caches of other processors in the shared memory multiprocessor system.

REFERENCES:
patent: 5526484 (1996-06-01), Casper et al.
patent: 6336169 (2002-01-01), Arimilli et al.
patent: 6611900 (2003-08-01), Patel et al.
patent: 6668309 (2003-12-01), Bachand et al.
patent: 6735675 (2004-05-01), Breuder et al.

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