Pipelined snooping of multiple L1 cache lines

Details Pipelined snooping of multiple L1 cache lines Pipelined snooping of multiple L1 cache lines

1997-06-12

2000-05-16

Nguyen, Hiep T

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711122, 711143, 711146, G06F 1208

Patent

active

060651016

ABSTRACT:
A cache system is provided for accessing set associative caches with no increase in critical path delay, for reducing the latency penalty for cache accesses, for reducing snoop busy time, and for responding to MRU misses and cache misses. A two level cache subsystem including an L1 cache and an L2 cache is provided. A cache directory is accessed for a second snoop request while a directory access from a first snoop request is being evaluated. During a REQUEST stage, a directory access snoop to the directory of the L1 cache is requested; and responsive thereto, during a SNOOP stage, the directory is accessed; during an ACCESS stage, the cache arrays are accessed while processing results from the SNOOP stage. If multiple data transfers are required out of the L1 cache, a pipeline hold is issued to the REQUEST and SNOOP stages, and the ACCESS stage is repeated. During a FLUSH stage, cache data read from the L1 cache during the ACCESS stage is sent to the L2 cache.

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