Pipelined-systolic single-instruction stream multiple-data strea

Details Pipelined-systolic single-instruction stream multiple-data strea Pipelined-systolic single-instruction stream multiple-data strea

1995-11-17

1998-08-04

An, Meng-Ai T.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

39580011, 39580016, 39580022, 395379, 711109, G06F 1580

Patent

active

057908796

ABSTRACT:
A pipelined-systolic SIMD array processing architecture includes an array of processing elements, registers-delays, and multiplexers. One or more of the registers-delays having one or more registers are added to the input and output ends of the processing elements for transferring data, with broadcasting and systolic methods being combined to transfer data into and out of the processing elements. By utilizing a single control unit, the functionalities of computation, shifting, transferring and accessing, achieving faster speed in data processing and accessing, and switching circuits may be added between the input/output ends of the processing elements and the registers-delay arrays, so as to transfer data even faster.

REFERENCES:
patent: 5218709 (1993-06-01), Fijany et al.
patent: 5361367 (1994-11-01), Fijany et al.
patent: 5404550 (1995-04-01), Horst
patent: 5581773 (1996-12-01), Glover
patent: 5581777 (1996-12-01), Kim et al.

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