Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-06-01
2008-12-02
Sough, Hyung (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S125000, C711S123000, C711S133000, C711S154000, C711S165000, C711S213000, C711S215000
Reexamination Certificate
active
07461205
ABSTRACT:
Mechanisms for performing useful computations during a software cache reload operation are provided. With the illustrative embodiments, in order to perform software caching, a compiler takes original source code, and while compiling the source code, inserts explicit cache lookup instructions into appropriate portions of the source code where cacheable variables are referenced. In addition, the compiler inserts a cache miss handler routine that is used to branch execution of the code to a cache miss handler if the cache lookup instructions result in a cache miss. The cache miss handler, prior to performing a wait operation for waiting for the data to be retrieved from the backing store, branches execution to an independent subroutine identified by a compiler. The independent subroutine is executed while the data is being retrieved from the backing store such that useful work is performed.
REFERENCES:
patent: 6751583 (2004-06-01), Clarke et al.
O'Brien John Kevin Patrick
O'Brien Kathryn
Chery Mardochee
International Business Machines - Corporation
Rifai D'Ann N.
Sough Hyung
Walder, Jr. Stephen J.
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