Performing overlapping burst memory accesses and interleaved mem

Details Performing overlapping burst memory accesses and interleaved mem Performing overlapping burst memory accesses and interleaved mem

1997-06-24

1999-11-16

Bragdon, Reginald G.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711168, 711169, 710 35, G06F 1208, G06F 1328, G06F 1316

Patent

active

059875704

ABSTRACT:
A high performance microprocessor bus protocol for improving system throughput. The bus protocol enables overlapping read burst and write burst bus transactions to a cache, and interleaved bus transactions during external fetch cycles for missed cache lines. The bus protocol is implemented in a system comprising a CPU, and a secondary cache. The secondary cache comprises an SRAM array cache, and a cache controller. The CPU contains an instruction pipeline and a primary cache system.

REFERENCES:
patent: 4169284 (1979-09-01), Hogan et al.
patent: 4794521 (1988-12-01), Ziegler et al.
patent: 5126975 (1992-06-01), Handy et al.
patent: 5179679 (1993-01-01), Shoemaker
patent: 5185871 (1993-02-01), Frey et al.
patent: 5222223 (1993-06-01), Webb, Jr. et al.
patent: 5293603 (1994-03-01), MacWilliams et al.
patent: 5325499 (1994-06-01), Kummer et al.
patent: 5416739 (1995-05-01), Wong

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