Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1995-11-13
1998-10-20
Lall, Parshotam S.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711214, 39580035, G06F 900
Patent
active
058260722
ABSTRACT:
Two embodiments of a digital signal processor are described. Each embodiment is configured with an instruction processing pipeline including an execute-write pipeline stage. When an instruction reaches the execute-write pipeline stage, the instruction is executed and the corresponding result is written to the specified destination. Additionally, the execute-write stage maintains a relatively short pipeline. One embodiment described herein employs an instruction set in which the destination of an instruction may be encoded within a subsequent instruction. The number of bits utilized to encode a particular instruction is reduced by the number of bits that would have specified the destination.
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Ho Horace C.
Knapp David J.
Daffer Kevin L.
Lall Parshotam S.
Merkel Lawrence J.
Oasis Design Inc.
Winder Patrica L.
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