Pipelined instruction cache and branch prediction mechanism ther

Details Pipelined instruction cache and branch prediction mechanism ther Pipelined instruction cache and branch prediction mechanism ther

1997-09-15

2000-08-08

Peikari, B. James

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711137, 711204, 711213, 712239, 712237, 712238, 712240, G06F 938

Patent

active

061015776

ABSTRACT:
A microprocessor includes an instruction cache having a cache access time greater than the clock cycle time employed by the microprocessor. The instruction cache is banked, and access to alternate banks is pipelined. The microprocessor also includes a branch prediction unit. The branch prediction unit provides a branch prediction in response to each fetch address. The branch prediction predicts a non-consecutive instruction block within the instruction stream being executed by the microprocessor. Access to the consecutive instruction block is initiated prior to completing access to a current instruction block. Therefore, a branch prediction for the consecutive instruction block is produced as a result of fetching a prior instruction block. A branch prediction produced as a result of fetching the current instruction block predicts the non-consecutive instruction block, and the fetch address of the non-consecutive instruction block is provided to the instruction cache access pipeline.

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