Performing a write cycle to memory in a multi-processor system

Details Performing a write cycle to memory in a multi-processor system Performing a write cycle to memory in a multi-processor system

1996-06-13

1998-09-15

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711220, 711217, 711211, 711143, G06F 1200

Patent

active

058095349

ABSTRACT:
In a method and system of performing a write cycle to a memory address in a multi-processor system, a first write cycle is initiated to the memory address, and a second write cycle is initiated to the memory address. Data from the first and second write cycles is merged, and the merged data is written to the memory address.

REFERENCES:
patent: 4298929 (1981-11-01), Capozzi
patent: 5341487 (1994-08-01), Derwin et al.
patent: 5347648 (1994-09-01), Stamm et al.
patent: 5404489 (1995-04-01), Woods et al.
patent: 5459842 (1995-10-01), Begun et al.
patent: 5463759 (1995-10-01), Ghosh et al.
patent: 5469555 (1995-11-01), Ghosh et al.
patent: 5553265 (1996-09-01), Abato et al.
patent: 5627993 (1997-05-01), Abato et al.
Compaq Computer ProLiant 2000, "QuickSpecs", Product Buletin, Doc. No. 041C/0595 (May 1995).
Compaq Computer ProLiant 4000, "QuickSpecs", Product Buletin, Doc. No. 043C/0595 (May 1995).

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