Multiple address sequence cache pre-fetching
Multiple address translations
Multiple changeable addressing mapping circuit
Multiple entry wavetable address cache to reduce accesses over a
Multiple page size address translation incorporating page...
Multiple page size address translation incorporating page...
Multiple patches to on-chip ROM in a processor with a...
Multiplexing DRAM control signals and chip select on a processor
Multiprobe instruction cache with instruction-based probe hint g
Multiprocessor cache coherence management
Multiprocessor system having a shared main memory accessible...
Multiprocessor system having mapping table in each node to map g
Multiprocessor system having plural memory locations for...
Multiprocessor system supporting multiple outstanding TLBI...
Multiprocessor system with retry-less TLBI protocol
Multithreaded processor having a source processor core to...
Mutually controlled match-line-to-word-line transfer circuit
Mutually controlled match-line-to-word-line transfer circuit
Native lookup instruction for file-access processor...
Netbufs: communication protocol packet buffering using paged...