Multiple entry wavetable address cache to reduce accesses over a

Details Multiple entry wavetable address cache to reduce accesses over a Multiple entry wavetable address cache to reduce accesses over a

1996-11-22

2000-04-04

Thai, Tuan V.

Electrical computers and digital processing systems: memory

Address formation

Combining two or more values to create address

710126, 711154, 711200, 711206, 711207, 711221, G06F 1200, G06F 1202, G06F 1210

Patent

active

060473657

ABSTRACT:
A method and apparatus for optimizing sample fetching in a peripheral component interconnect (PCI) environment. In one embodiment the present invention generates a first sample page base address corresponding to a first part of a first address received from a digital signal processor (DSP). The present invention also generates a second sample page base address corresponding to a first part of a second address received from the DSP. The first and second generated sample page base addresses are then stored in respective first and second locations within a multiple entry sample page base address cache which can be accessed by the DSP without accessing a PCI bus. The first part of the first address is compared to a first part of a third address. Provided that the first part of the first address and the first part of the third address are the same, the present invention combines a second portion of the third address sent from the DSP with the first generated sample page base address stored in the multiple entry sample page base address cache. The first part of the second address is also compared with the first part of the third address. Provided that the first part of the second address and the first part of the third address are the same, the present invention combines the second portion of the third address sent from the DSP with the second generated sample page base address stored in the multiple entry sample page base address cache. In so doing, the present invention generates a complete address of a sample to be fetched without accessing the PCI bus.

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Handy, Jim, "The Cache Memory Book", Academic Press, ISBN 0-12-322985-5, p. 15, 1993.
PCI Special Interest Group, "PCI Local Bus Specification, Revision 2.1", Portland Oregon 97214, Jun. 1, 1995.

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