Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2005-09-09
2008-11-18
Kim, Matt (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S202000, C711S203000, C711S204000, C711S205000, C711S206000
Reexamination Certificate
active
07454590
ABSTRACT:
In one embodiment, a processor comprises a plurality of processor cores and an interconnect to which the plurality of processor cores are coupled. Each of the plurality of processor cores comprises at least one translation lookaside buffer (TLB). A first processor core is configured to broadcast a demap command on the interconnect responsive to executing a demap operation. The demap command identifies one or more translations to be invalidated in the TLBs, and remaining processor cores are configured to invalidate the translations in the respective TLBs. The remaining processor cores transmit a response to the first processor core, and the first processor core is configured to delay continued processing subsequent to the demap operation until the responses are received from each of the remaining processor cores.
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Office Action from U.S. Appl. No. 11/222,577, mailed Aug. 22, 2007.
Grohoski Gregory F.
Jordan Paul J.
Shah Manish K.
Kim Matt
Merkel Lawrence J.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Patel Hetul
Sun Microsystems Inc.
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