Mutually controlled match-line-to-word-line transfer circuit

Details Mutually controlled match-line-to-word-line transfer circuit Mutually controlled match-line-to-word-line transfer circuit

1996-04-29

1999-04-13

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711206, 711207, 711108, 711128, 365 49, 36523006, G06F 1208

Patent

active

058939296

ABSTRACT:
A circuit for transferring a logic value from a content addressable memory (CAM) having a plurality of match lines to a random access memory (RAM) having a plurality of word lines. A first logic gate has an input coupled to a first match line of the plurality of match lines, and a second logic gate has an input coupled to a second match line of the plurality of match lines. A first switch is coupled between an output of the first logic gate and a first word line, and a second switch is coupled between an output of the second logic gate and a second word line. The first switch is controlled by the output of the second logic gate such that the first switch is opened when the second match line has a second logic value and closed when the second match line has a first logic value. The second switch is controlled by the output of the first logic gate such that the second switch is opened when the first match line has the second logic value and closed when the first match line has the first logic value.

REFERENCES:
patent: 4559618 (1985-12-01), Houseman et al.
patent: 5299147 (1994-03-01), Hoist
patent: 5396448 (1995-03-01), Takayanagi et al.
patent: 5602770 (1997-02-01), Ohira
patent: 5602795 (1997-02-01), Sandhu
patent: 5617348 (1997-04-01), Maguire
patent: 5640534 (1997-06-01), Liu et al.

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