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Hardware assistance for shadow page table coherence with...

Electrical computers and digital processing systems: memory – Address formation – Address mapping
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Hardware demapping of TLBs shared by multiple threads

Electrical computers and digital processing systems: memory – Address formation – Address mapping
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Hardware emulation of parallel ATA drives with serial ATA...

Electrical computers and digital processing systems: memory – Address formation – Address mapping
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Hash Cam having a reduced size memory array and its application

Electrical computers and digital processing systems: memory – Address formation – Hashing
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Hash optimization system and method

Electrical computers and digital processing systems: memory – Address formation – Hashing
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Hash tables

Electrical computers and digital processing systems: memory – Address formation – Hashing
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Hash technique eliminating pointer storage to reduce RAM size

Electrical computers and digital processing systems: memory – Address formation – Hashing
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Hashing and serial decoding techniques

Electrical computers and digital processing systems: memory – Address formation – Incrementing – decrementing – or shifting circuitry
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Hashing and serial decoding techniques

Electrical computers and digital processing systems: memory – Address formation – Incrementing – decrementing – or shifting circuitry
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Hashing method and apparatus

Electrical computers and digital processing systems: memory – Address formation – Hashing
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Heap memory management

Electrical computers and digital processing systems: memory – Address formation – Address mapping
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Hierarchical fully-associative-translation lookaside buffer...

Electrical computers and digital processing systems: memory – Address formation – Address mapping
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Hierarchical storage management system

Electrical computers and digital processing systems: memory – Address formation – Address mapping
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High performance cache directory addressing scheme for...

Electrical computers and digital processing systems: memory – Address formation – Combining two or more values to create address
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High performance mechanism for managing allocation of virtual me

Electrical computers and digital processing systems: memory – Address formation – Address mapping
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High performance memory device-state aware chipset prefetcher

Electrical computers and digital processing systems: memory – Address formation – Generating prefetch – look-ahead – jump – or predictive address
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High speed address sequencer

Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses
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High speed four-to-two carry save adder

Electrical computers and digital processing systems: memory – Address formation – Combining two or more values to create address
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High speed module address generator

Electrical computers and digital processing systems: memory – Address formation – Incrementing – decrementing – or shifting circuitry
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High speed translation lookaside buffer employing content addres

Electrical computers and digital processing systems: memory – Address formation – Address mapping
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