Gate reuse methodology for diffused cell-based IP blocks in...

Gate-length biasing for digital circuit optimization

Gated clock conversion

Gated clock design supporting method, gated clock design...

Gated clock generating circuit and method of modifying the...

General purpose shape-based layout processing scheme for IC...

Generalized theory of logical effort for look-up table based...

Generating a base curve database to reduce storage cost

Generating a function within a logic design using a dialog box

Generating a logic design

Generating a split power plane of a multi-layer printed...

Generating an instance-based representation of a design...

Generating an optical model for lens aberrations

Generating candidate architectures for an architectural...

Generating components on a programmable device using a...

Generating components on a programmable device using a...

Generating constraint preserving testcases in the presence...

Generating cores using secure scripts

Generating fast logic simulation models for a PLD design...

Generating hardware interfaces for designs specified in a...