Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-04-13
2003-01-07
Nelms, David (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06505327
ABSTRACT:
BACKGROUND
1. Field of the Invention
The invention relates to the process of designing an integrated circuit. More specifically, the invention relates to a method and an apparatus for generating an instance-based representation of a set of geometrical features that comprise a layout of a circuit on a semiconductor chip in order to speed up subsequent operations on the layout.
2. Related Art
Recent advances in integrated circuit technology have largely been accomplished by decreasing the feature size of circuit elements on a semiconductor chip. As the feature size of these circuit elements continues to decrease, circuit designers are forced to deal with problems that arise as a consequence of the optical lithography process that is typically used to manufacture integrated circuits. This optical lithography process generally begins with the formation of a photoresist layer on the surface of a semiconductor wafer. A mask composed of opaque regions, which are generally formed of chrome, and light-transmissive clear regions, which are generally formed of quartz, is then positioned over this photo resist layer coated wafer. (Note that the term “mask” as used in this specification is meant to include the term “retical.”) Light is then shone on the mask from a visible light source or an ultraviolet light source.
This light is generally reduced and focussed through an optical system that contains a number of lenses, filters and mirrors. The light passes through the clear regions of the mask and exposes the underlying photoresist layer. At the same time, the light is blocked by opaque regions of mask, leaving underlying portions of the photoresist layer unexposed.
The exposed photoresist layer is then developed, typically through chemical removal of the exposed
on-exposed regions of the photoresist layer. The end result is a semiconductor wafer with a photoresist layer having a desired pattern. This pattern can then be used for etching underlying regions of the wafer.
One problem that arises during the optical lithography process is “line end shortening” and “pullback”. For example, the upper portion of
FIG. 1
illustrates a design of a transistor with a polysilicon line
102
, running from left to right, that forms a gate region used to electrically couple an upper diffusion region with a lower diffusion region. The lower portion of
FIG. 1
illustrates the actual printed image that results from the design. Note that polysilicon line
102
has been narrowed using optical phase shifting in order to improve the performance of the transistor by reducing the resistance through the gate region.
Also note that because of optical effects and resist pullback there is a significant amount of line end shortening. This line end shortening is due to optical effects that cause the light to expose more of the resist under a line end than under other portions of the line.
In order to compensate for line end shortening, designers often add additional features, such as “hammer heads,” onto line ends (see top portion of FIG.
2
). As is illustrated in the bottom portion
FIG. 2
, these additional features can effectively compensate for line end shortening in some situations.
These additional features are typically added to a layout automatically during a process known as “optical proximity correction” (OPC). However, the optical proximity correction process can be complicated by the fact that a layout for a semiconductor chip is often stored in a standard hierarchical format, such as GDSII stream format.
For example,
FIGS. 3A
,
3
B and
3
C illustrate how a layout, T, can be composed of a sub-cell A and a sub-cell B, wherein the sub-cell A further includes a sub-cell C.
FIG. 3A
illustrates a nodal representation of this hierarchy and
FIG. 3B
illustrates a corresponding graphical representation.
FIG. 3C
presents a specification of the layout in code form. In this form, the layout, T, includes a reference list. This reference list includes a reference to cell A along with an associated transformation, T
A
, and a reference to cell B along with an associated transformation, T
B
. Similarly, the layout for cell A includes geometrical features associated with cell A along with a reference cell C. This reference to cell C is accompanied by a transformation of cell C with respect to A, T
CA
. The layouts for cell B and cell C include geometrical features associated with cell B and cell C, respectively.
One problem with applying OPC to a hierarchical representation of a layout is that interactions between nodes within the hierarchical representation can cause erroneous correction can take place. For example, referring to
FIG. 4
, a cell T, is composed of a cell A and a cell B. However, if OPC is applied to cell A and cell B separately within the hierarchical representation, bogus corrections can take place as is illustrated in step
3
.
Note that these bogus corrections are unnecessary because the neighboring cells A and B eliminate the need for the hammerheads between the cells A and B. In order to remove these bogus corrections, an additional bogus correction removal step
4
is required. This bogus correction removal step may be accomplished by storing “negative features” to erase the bogus features at various nodes within the hierarchy.
Another way to eliminate the bogus correction problem is to collapse the hierarchy down into a single monolithic layout, and then to apply OPC to the single monolithic layout. Unfortunately, this technique can be prohibitively slow because OPC must be applied to the entire layout.
In contrast, by using a hierarchical form of the layout, once OPC is applied to the layout of a specific cell, the result can be applied to all instances of the cell without repeating the OPC process for each cell. Unfortunately, interactions with neighboring nodes and parent nodes can cause the above-described bogus correction problems.
What is needed is a method and an apparatus for performing a computational operation, such as OPC, on a hierarchical representation of a layout without performing the computational operation over the entire layout, and without the above-described problems associated with using a hierarchical representation.
SUMMARY
One embodiment of the invention provides a system for generating an instance-based representation of a set of geometrical features that comprise a layout of a circuit on a semiconductor chip. This system operates by receiving a design hierarchy specifying the layout of the circuit, wherein the design hierarchy includes a set of hierarchically organized nodes. Within this design hierarchy, a given node specifies a geometrical feature, which can be comprised of lower-level geometrical features. These lower-level geometrical features are represented by lower-level nodes that appear under the given node in the design hierarchy. Furthermore, the layout of the given node is specified by a first cell, which in turn specifies the layout of one or more nodes in the design hierarchy. For each node within the design hierarchy, the system determines how interactions with the node's siblings and/or parent, and possibly with other surrounding geometries, change the layout of the node as specified by the first cell. If the changes result in a new node for which no instance has been created, the system creates a new instance for the node.
In one embodiment of the invention, the system additionally collapses the design hierarchy, so that each node in the design hierarchy is represented by a specific node instance that is not affected by higher-level or neighboring nodes in the design hierarchy. Note that a given node is said to be “affected” by high-level or neighboring nodes if other instances of the given node have different geometries within a proximity region around the other instances.
In one embodiment of the invention, the system additionally performs an analysis on each node instance within the instance-based representation of the layout without having to consider effects of higher-level or neighboring nodes in the design hierarchy. In a variation
Hoang Quoc
Nelms David
Numerical Technologies Inc.
Park Vaughan & Fleming LLP
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