Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-02-09
2009-10-06
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07600209
ABSTRACT:
Mechanisms for generating constraint preserving testcases in the presence of dead-end constraints are provided. A balance between precision and computational expense in generating the testcases is achieved by establishing a sliding window of constraint solving for a selected number of K time-steps in the future from a current time-step. The testcases solve for the constraints for the next K time-steps at every state of a netlist instead of just trying to solve the constraint for the present time-step. K is determined by determining, for each input, either a minimum length path depth or maximum length depth path from the input to the constraint. The largest depth value for the inputs to the netlist is then utilized as the depth for the netlist. This depth then is used to define the width of the sliding window of constraint solving.
REFERENCES:
patent: 2005/0198597 (2005-09-01), Zhu et al.
patent: 2006/0206842 (2006-09-01), Baumgartner et al.
Biere et al., “SAT and ATPG: Boolean engines for formal hardware verification”, IEEE, 2002, 4 pages.
Yuan et al., “Modeling Design Constraints and Biasing in Simulation Using BDDs”, IEEE/ACM International Conference on Computer Aided Design, 1999, 6 pages.
Baumgartner Jason R.
Kanzelman Robert L.
Mony Hari
Paruthi Viresh
Dimyan Magid Y
Gerhardt Diana R.
International Business Machines - Corporation
Siek Vuthe
Walder, Jr. Stephen J.
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