Gate-length biasing for digital circuit optimization

Details Gate-length biasing for digital circuit optimization Gate-length biasing for digital circuit optimization

2005-06-03

2008-10-21

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07441211

ABSTRACT:
Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology replaces a nominal gate-length of a transistor with a biased gate-length, where the biased gate-length includes a bias length that is small compared to the nominal gate-length. In an exemplary embodiment, the bias length is less than 10% of the nominal gate-length.

REFERENCES:
patent: 6954918 (2005-10-01), Houston
patent: 7222328 (2007-05-01), Hasumi et al.
Gupta, P. et al., “Joining the Design and Mask Flows for Better and Cheaper Masks,” Proc. 24thBACUS Symposium on Photomask Technology and Management, Sep. 2004, 12 pages.
Gupta, P. et al., “Selective Gate-Length Biasing for Cost-Effective Runtime Leakage Control,” DAC 2004, Jun. 7-11, 2004, pp. 327-330, San Diego, CA.
Clark, L. et al., “Managing Standby and Active Mode Leakage Power in Deep Sub-micron Design”, Proceedings IEEE International Symposium on Low Power Electronic Design, 2004, pp. 275-279.

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