Generating a split power plane of a multi-layer printed...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07124390

ABSTRACT:
Methods and apparatuses generate a split power plane for a multiplayer printed circuit board (PCB). An aspect of the invention supports the generation of a split power plane by constructing wireframes corresponding to each of the power voltages. If a crossover between different voltage wireframes exists, at least one of the voltage wireframes may be modified in order to eliminate the crossover. With another aspect of the invention, a trace layout, corresponding to the wireframe, is constructed in accordance with electrical current requirements, e.g. average electrical current and peak electrical current, of the associated components. With another aspect of the invention, a plane that contain the traces that associated with a power voltage may be enhanced by increasing the associated area of the layout in accordance with the available area of the split power plane. The enhancement of a plane may be prioritized in accordance with peak electrical current that is associated with the plane.

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T. Hubing et al., Preliminary Embedded Capacitance Measurement Results, NCMS Embedded Capacitance Project, Oct. 23, 1999, 25 pp.
Todd Hubing et al., Power Bus Noise Reduction Using Power Islands in Printed Circuit Board Designs, University of Missouri-Rolla Electromagnetic Compatibility Laboratory, Nov. 11, 1999, 11 pp.
Todd Hubing, Prof., University of Missouri-Rolla, PWB Power Bus Structures: Theory and Design, University of Missouri-Rolla Electromagnetic Compatibility Laboratory, IEEE EMC Society Rocky Mountain Chapter, Nov. 11, 1999, 24 pp.
Istvan Novak et al., SUN Microsystems, Inc., Simulating Complex Power-Ground Plane Shapes With Variable-Size Cell SPICE Grids, Manuscript for the 11thTopical Meeting on Electrical Performance of Electronic Packaging Oct. 21-23, 2002, Monterey, CA.

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