Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-10-04
2005-10-04
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C717S140000, C717S155000, C717S156000, C717S161000
Reexamination Certificate
active
06952817
ABSTRACT:
A method of processing a general-purpose, high level language program to determine a hardware representation of the program can include compiling the general-purpose, high level language program to generate a language independent model (105, 110, and115). The language independent model can be scheduled such that each component is activated when both control and valid data arrive at the component (120). An interface structure specifying a hardware interface through which devices external to the language independent model interact with a physical implementation of the language independent model can be defined and included in the language independent model (200, 300, 400).
REFERENCES:
patent: 6625797 (2003-09-01), Edwards et al.
patent: 6651228 (2003-11-01), Narain et al.
U.S. Appl. No. 10/310,260, filed Dec. 4, 2002, Edwards et al.
U.S. Appl. No. 10/310,362, filed Dec. 4, 2002, Edwards et al.
U.S. Appl. No. 10/310,520, filed Dec. 4, 2002, Miller et al.
Edwards Stephen G.
Harris Jonathan C.
Jensen James E.
Kollegger Andreas B.
Miller Ian D.
King John
Meles Pablo
Siek Vuthe
Xilinx , Inc.
LandOfFree
Generating hardware interfaces for designs specified in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Generating hardware interfaces for designs specified in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Generating hardware interfaces for designs specified in a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3479499