Verification of sequential circuits with same state encoding

Verification support device, verification support method,...

Verification using simultaneous and inductive SAT algorithms

Verification utilizing instance-based hierarchy management

Verifying a process margin of a mask pattern using...

Verifying an IC layout in individual regions and combining...

Verifying decoupling capacitance using a maximum flow...

Verifying hardware in its software context and vice-versa

Verifying logic synthesizers

Verifying on-chip decoupling capacitance

Verifying one or more properties of a design using SAT-based...

Verifying proximity of ground metal to signal traces in an...

Verifying proximity of ground vias to signal vias in an...

Verilog to vital translator

Versatile multiplexer-structures in programmable logic using...

Versatile multiplexer-structures in programmable logic using...

Vertex based layout pattern (VEP): a method and apparatus...

Via enclosure rule check in a multi-wide object class design...

Via redundancy based on subnet timing information, target...

Via/BSM pattern optimization to reduce DC gradients and pin...