Verilog to vital translator

Details Verilog to vital translator Verilog to vital translator

2001-10-31

2003-12-23

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06668359

ABSTRACT:

REFERENCE TO COMPUTER PROGRAM LISTING APPENDIX
The following computer program listing files are submitted on a compact disc and are incorporated herein by reference:
NAME
CREATION DATE
SIZE (bytes)
Appendix.txt
Aug. 25, 2003
136,921
FIELD OF THE INVENTION
The present invention relates generally to electronic design automation (EDA) tools. More specifically, but without limitation thereto, the present invention relates to translating a description of a circuit from a design model format into an EDA format.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method includes receiving as inputs a user defined primitives map file, a truth table map file, a gate primitives map file, a register transfer level description file of a library cell, a standard delay format file, and a pin order information file for the register transfer level code model; creating data structures for a VITAL model; parsing at least one of the user defined primitives map file, the truth table map file, the gate primitives map file, the register transfer level description file, and the standard delay format file to generate an equivalent VITAL model in the data structures created for the VITAL model wherein the VITAL model is functionally equivalent to the register transfer level code model; and generating as output a VITAL model file from the data structures created for the VITAL model.


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