Vertex based layout pattern (VEP): a method and apparatus...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

06892367

ABSTRACT:
A method to describe a circuit pattern comprises identifying vertices and those edges of the circuit pattern that are not incident with any vertex contained within a region of interest within the circuit pattern. The region of interest includes a portion of a polygon that is less than the entire polygon. The vertices and edges of the circuit pattern are compared to a predetermined set of known vertices and edges. A match may be used to identify an acceptable circuit or a defective circuit.

REFERENCES:
patent: 5613102 (1997-03-01), Chiang et al.
Paper 8.10, “Manufacturability Analysis of 0.25-micron IC Topography Based on Novel Representation Using Repeatability of Layout Patterns”, Techcon 1998.
Niewczas et al., “A Pattern Matching Algorithm for Verification and Analysis of Very Large IC Layouts”, Proc. of International Symposium of Physical Design, Apr. 1998, Monterey, CA, pp. 129-134.
Niewczas et al., “An Algorithm for Determining Repetitive Patterns in Very Large IC Layouts”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, No. 4, pp. 292-501, Apr. 1999.
Niewczas et al., “Chip Scale 3-D Topography Synthesis”, Proc. of 23rdSymposium on Optical Microlithography, SPIE vol. 3334, Feb. 1998.
Niewczas et al., Disclosure of Invention, A Method for Finding Repetitive Patterns in VLSI Mask Layout Data, CMU Technology Transfer Office, no date.
Niewczas et al., “Regularity Extraction from VLSI Mask Layout”, Research Report, CMU, Pittsburgh, Jul. 10, 1999, pp. 1-62.
Niewczas et al., “Vicinity Pattern Matching Algorithm for Processing of IC Mask Layouts”, SRC Report C99014 (Research Report No. CMUCAD-98-47), Carnegie Mellon University, Dec. 1998.

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