Verification support device, verification support method,...

Details Verification support device, verification support method,... Verification support device, verification support method,...

2006-08-16

2008-12-09

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07464363

ABSTRACT:
A verification support device supports logic verification of a design object corresponding to modified sequence diagrams obtained by modifying sequence diagrams expressing processes of a design object in a chronological order. A diagram extracting unit extracts the modified sequence diagrams. A modified process detecting unit detects modified processes by comparing the sequence diagrams before modification and the sequence diagrams after modification. Based on the modified processes, an applicability determining unit determines whether test benches used for a regression test of the design object of the sequence diagrams before modification is applicable to a regression test of the design object of the sequence diagrams after modification. A test bench output unit outputs test benches based on a result of determination by the applicability determining unit.

REFERENCES:
patent: 6904577 (2005-06-01), Schubert et al.
patent: 7263478 (2007-08-01), Tsuchiya
patent: 2003/0125920 (2003-07-01), Matsuoka et al.
patent: 2004/0015798 (2004-01-01), Davidson et al.
patent: 2000-258511 (2000-09-01), None
patent: 2002-073724 (2002-03-01), None
patent: 2002-73724 (2002-03-01), None
Office Action issued in corresponding Japanese Patent Application No. 2006-510564, mailed on Jan. 15, 2008.

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