Verifying on-chip decoupling capacitance

Details Verifying on-chip decoupling capacitance Verifying on-chip decoupling capacitance

2001-08-17

2003-09-09

Chapman, John E. (Department: 2858)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C324S548000

Reexamination Certificate

active

06618845

ABSTRACT:

BACKGROUND OF INVENTION
As the frequencies of modem computers continue to increase, power consumption by such computers increases accordingly. Because power consumption needs of various components, e.g., microprocessors, within a computer system have to be met in order to sustain the increasing speeds of modem computers, the providing of power to the components within the computer system has to be accurate and predictable.
A power supply for a computer system component, such as a computer chip, typically resides at some distance from discrete elements on the chip. Therefore, a discrete element, such as a driver (transistor), may not get power (via current) as soon as it needs it. In order to combat this potential performance inhibition, one or more decoupling capacitors are positioned across a driver to store charge from the power supply for distribution, when needed, to one or more drivers. The power supply, along with the drivers and decoupling capacitors, form a power grid on the computer chip. Thus, in essence, groups of discrete elements on the chip may have their own power supplies.
It follows that an important concern for designers is to ensure that each driver has enough decoupling capacitance. Referring to
FIG. 1
a,
to verify that there is enough decoupling capacitance on a computer chip (
10
), a designer selects one of several areas (
11
), i.e., blocks, on the computer chip (
10
), chooses a particular signal in that area, and verifies that there is enough decoupling capacitance for the drivers associated with that particular signal. However, this verification process does not guarantee that there is enough decoupling capacitance within a given distance of a particular driver.
Such a guarantee is important because driver delay depends on how quickly charge, i.e., power, is transferred from a power supply or decoupling capacitor to a particular driver. Typically, charge transfer from a power supply is slower than charge transfer from a decoupling capacitor, and thus, it is imperative that there be enough decoupling capacitance for the particular driver. The faster a driver gets power, the faster a signal driven by the driver can switch.
FIG. 1
b
shows an expansion (
12
) of one of the areas (
11
) on the computer chip (
10
). The expanded area (
12
) has decoupling capacitors (
14
) and drivers (
16
). Further, power supply lines (
14
) provide power to the decoupling capacitors (
14
) and drivers (
16
). In turn, the drivers (
16
) drive groups of discrete elements (not shown) on the computer chip (
10
) by providing signals to them as needed. The decoupling capacitors (
14
) store charge from the power supply lines (
14
) for distribution, when needed, to the drivers (
16
).
Typically, a designer selects a signal (not shown) residing in the area (
12
), and determines whether there are enough decoupling capacitors (
14
), i.e., enough decoupling capacitance, for the drivers (
16
) associated with the selected signal in the selected area (
12
). In other words, the designer compares the ratio between the total number of decoupling capacitors and drivers in the selected area (
12
).
The ability of a decoupling capacitor to adequately distribute charge to a particular driver depends on the distance between the decoupling capacitor and the particular driver. Thus, in order for a decoupling capacitor to distribute charge to a driver that resides relatively far away from the decoupling capacitor, the decoupling capacitor has to be large enough to be able to sufficiently distribute charge to the driver. It follows that the area used by a decoupling capacitor is proportional to a particular driver. This relationship results in a need for a balance between providing adequate charge to ensure proper driver performance and meeting area restrictions on a computer chip.
SUMMARY OF INVENTION
According to one aspect of the present invention, a method for determining decoupling capacitance on a computer chip comprises selecting a driver on the computer chip, selecting a first decoupling capacitor, where the first decoupling capacitor is within a specified distance of the driver, forming a linear equation based on the driver and the first decoupling capacitor, wherein a linear problem comprises the linear equation, and solving the linear problem to determine decoupling capacitance on the computer chip.
According to another aspect, a software tool that determines decoupling capacitance on a computer chip having a driver and at least one decoupling capacitor comprises a first portion that selects a driver, a second portion that selects a first decoupling capacitor, where the first decoupling capacitor is within a specified distance of the driver, a third portion that forms a linear equation based on the driver and the first decoupling capacitor, where a linear problem comprises the linear equation, and a last portion that solves the linear problem to verify decoupling capacitance on the computer chip.
According to another aspect, a method for designing an integrated circuit, comprises determining a decoupling capacitance need of the integrated circuit, verifying an amount of decoupling capacitance on the integrated circuit, where verifying the amount of decoupling capacitance comprises forming and solving a linear problem, and resizing at least one decoupling capacitor based on a solution of the linear problem.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.


REFERENCES:
patent: 6175949 (2001-01-01), Gristede et al.
patent: 2003/0034783 (2003-02-01), Thorp et al.

Affiliated with

Also associated with

Rating

Verifying on-chip decoupling capacitance does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Verifying on-chip decoupling capacitance, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Verifying on-chip decoupling capacitance will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3002637