Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-06-10
2008-11-25
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C700S097000, C700S120000, C700S121000, C430S005000, C378S035000
Reexamination Certificate
active
07458058
ABSTRACT:
Verifying a process margin for a mask pattern includes receiving the mask pattern for patterning features on a semiconductor wafer. The mask pattern is modified according to a wafer pattern model operable to estimate a wafer pattern resulting from the mask pattern. An intermediate stage model is selected to apply to a portion of the mask pattern, where the intermediate stage model is operable to estimate an intermediate stage of the wafer pattern. A process margin of the portion is verified by selecting a test of the intermediate stage model, and performing the test on the portion to verify the process margin of the portion.
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Aton Thomas J.
McKee William R.
Parikh Ashesh
Brady III Wade J.
Kik Phallaka
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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