Via/BSM pattern optimization to reduce DC gradients and pin...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

11184350

ABSTRACT:
A carrier for an electronic device such as an integrated circuit chip is designed by assigning two different voltage domains to two separate areas of the contact surface of the carrier, while providing a common electrical ground for both voltage domains. The integrated circuit chip may be a microprocessor having a nominal operating voltage, and the different voltages of the two voltage domains are both within the tolerance range of the nominal operating voltage but one of the voltage domains is aligned with a high power density area of the microprocessor (e.g., the microprocessor core) and provides a slightly greater voltage. The higher power voltage domain preferably has a ratio of voltage pins to ground pins that is greater than one.

REFERENCES:
patent: 6462976 (2002-10-01), Olejniczak et al.
patent: 6806563 (2004-10-01), Libous et al.
patent: 6971160 (2005-12-01), Welch et al.
patent: 2004/0183184 (2004-09-01), Libous et al.
patent: 2006/0059373 (2006-03-01), Fayad et al.

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