Via redundancy based on subnet timing information, target...

Details Via redundancy based on subnet timing information, target... Via redundancy based on subnet timing information, target...

2007-10-30

2007-10-30

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

10907496

ABSTRACT:
Methods, systems and program products are disclosed that prioritize each target via for via redundancy based on at least one of the following: subnet timing information, a distance of a target via along a path from a driving source and a target via net/subnet characteristic, and attempt to add a redundant via to each target via based on the prioritization. The invention improves overall yield and reduces timing sensitivity to AC-related defects.

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