Boosting simulation performance by dynamically customizing...
Bottom-up approach for synthesis of register transfer level...
Boundary scan cell architecture with complete set of...
Boundary-scan cells with improved timing characteristics
Broken symmetry for optimization of resource fabric in a...
Buffer cell insertion and electronic design automation
Buffer insertion with adaptive blockage avoidance
Buffer placement with respect to data flow direction and...
Buffering circuit embedded in an integrated circuit device...
Buffering technique using structured delay skewing
Buffering tree analysis in mapped design
Building binary decision diagrams efficiently in a...
Building integrated circuits using a common database
Building integrated circuits using a common database
Bus architecture for system on a chip
Bus I/O placement guidance
Bus representation for efficient physical synthesis of...
BWB transmission wiring design system
Byte slice based DDR timing closure