Bus I/O placement guidance

Details Bus I/O placement guidance Bus I/O placement guidance

2001-11-30

2003-11-25

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06654941

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for implementing I/O circuitry generally and, more particularly, to a method and/or architecture for placement of bus I/O circuitry.
BACKGROUND OF THE INVENTION
Designers of programmable logic devices (PLDs) need an efficient system to fix pinout designs to printed circuit boards (PCBS). For example, once a PCB is manufactured, Designers typically recompile PLD designs to fit the pinout constraint of the PCB. Furthermore, if the Designer has specific routing guidances to follow (i.e., if the PLD connects to a PCI edge connector or if a data bus connects to an external memory), the Designer is only given control over individual pins. For example, the Designer can only specify the exact location of a limited number of pins.
Conventional technologies for pinout assignment consist of (i) exact specified pin placement, where every I/O pin is uniquely specified and (ii) automatic pin placement, where the pinout is determined by placer software. Such conventional technologies have the following limitations (i) if the Designer allows the placer to define the pinout, PCB routing will be complicated and non-optimal, (ii) if the Designer defines the pinout, the timing of the PLD might not be optimal (i.e., functional success, timing failure), (iii) if the Designer defines the pinout, the PLD design might not fit in the PLD due to fundamental architectural limitations (i.e., functional failure), and (iv) if the Designer defines the pinout and decides to manually iterate multiple pinouts to improve PCB routing and/or timing, critical design time is wasted and the design might not be optimized.
Referring to
FIG. 1
, a PCB
10
with a PLD
12
connected to a PCI edge connector
14
is shown illustrating undesirable routing. A PCI edge connector is an example of application specific pin placement. A portion of the PCI connector pinout from the PCI specification, Version 2.2 (published December 1998 and hereby incorporated by reference in its entirety) is shown in the following TABLE 1:
TABLE 1
5 V System Environment
PIN
Side B
Side A
1
−12 V
TRST#
2
TCK
+12 V
3
Ground
TMS
4
TDO
TDI
5
+5 V
+5 V
6
+5 V
INTA#
7
INTB#
INTC#
8
INTD#
+5 V
9
PRSNT1#
Reserved
10
Reserved
+5 V
(I/O)
11
PRSNT2#
Reserved
12
Ground
Ground
13
Ground
Ground
14
Reserved
3.3 Vaux
15
Ground
RST#
16
CLK
+5 V
(I/O)
17
Ground
GNT#
18
REQ#
Ground
19
+5 V
(I/O)
PME#
20
AD[31]
AD[30]
21
AD[29]
+3.3 V
22
Ground
AD[28]
23
AD[27]
AD[26]
24
AD[25]
Ground
25
+3.3 V
AD[24]
26
C/BE[3]#
IDSEL
27
AD[23]
+3.3 V
28
Ground
AD[22]
29
AD[21]
AD[20]
PCB Designers attempt to avoid crossovers, while routing the programmable I/O of the PLD
12
to the PCI edge connector
14
. Avoiding crossover routing reduces the number of vias, which are impedance discontinuities. Routing without vias allows signal traces to closely approximate a transmission line (i.e., continuous uniform cross-section), since the traces do not cross each other.
Referring to
FIG. 2
, a segmented I/O architecture
20
is shown. The pinout of a PLD
21
is defined prior to the compilation of the logic inside the PLD
21
. Often, the Designer specifies a pinout that does not provide optimum timing performance or is not architecturally compatible with the I/O architecture of the PLD
21
. Therefore, some PCI bus signals are in one routing channel (A) and some PCI bus signals are in another routing channel (B). The logic clusters
22
a
-
22
n
are not able to receive all the PCI bus signals without using the routing switches (C). As a result, the associated timing parameters (i.e., setup, state-to-state, clock-to-output, etc.) are larger (worse) than the maximum performance specifications of the device
20
.
Referring to
FIG. 3
, an I/O block
30
is shown. The output control channel (OCC)
32
is common to each I/O block (i.e., the OCC
32
is a banked resource). Therefore, only two unique logic-driven output enable (OE) conditions can be used in a given I/O block. For example, if a system Designer defines a pinout such that signals connected to an I/O block
30
require three unique logic-driven OE conditions, the placer software will not be able to complete placement of the design. The Designer is then forced to move a portion of the I/O logic
30
, and re-try the compilation/placement process.
Referring to
FIG. 4
, a simplified interface circuit
40
is shown illustrating a desirable I/O mapping. The circuit
40
illustrates a desirable mapping of the framer
42
and the serializer/deserializer (SERDES)
44
. The circuit
40
routes the data bus between the PLD
42
and the SERDES
44
by laying the traces in order. However, if the placer software determines the pinout arbitrarily (i.e., if the Designer does not specify any pin constraints), the placement is not guaranteed to be orderly.
Referring to
FIG. 5
, a simplified interface circuit
50
is shown illustrating an undesirable I/O mapping. The circuit
50
illustrates an undesirable mapping of the framer
52
to the SERDES
54
. Since the placer software determined the pinout of the circuit
50
arbitrarily, the system
50
is disorderly. The Designer must correct the design. The Designer can (i) perform PCB layout with traces that cross each other (i.e., use vias extensively) or (ii) change the pinout of the PLD
52
to conform to the pinout of the SERDES device
54
. Since vias are to be avoided, the Designer has to individually assign the signals of the PLD
52
to align with the pinout of the SERDES
54
. For example, the Designer must specify that the “Data
0
” pin connects to “pin
58
” and the “Data
1
” pin connects to “pin
59
”.
The assignment process is manual and not efficient. Furthermore, if the Designer encounters an architectural limitation during the assignment process, such as the OCC OE constraint (i.e., the circuit
30
), the Designer will have to determine a new pinout that meets the timing requirements, PCB layout requirements, and architectural limitations of the PLD in use.
When the Designer specifies a hard pinout prior to compilation, the placer software must meet timing constraints for a pinout that can be non-optimal from a timing perspective. As a result, the software has less freedom to determine logic placement to meet the timing constraints imposed by the Designer. When the Designer allows the pins to float during compilation, the placer has no pinout guidance and the Designer is forced to route the PCB in a non-optimal manner (i.e., with traces crossing each other).
Current PLD pinout design techniques either (i) define the PLD pinout before the code for the PLD is written or (ii) define the target PLD code and then perform the board layout. In either case, the Designer is forced to move signal assignments one-by-one to optimize the overall design.
It is generally desirable to provide automated bus I/O placement guidance for PLDs on PCBs that optimizes routing and timing at a minimal cost.
SUMMARY OF THE INVENTION
The present invention concerns a method for relative placement guidance, comprising the steps of (A) placing a plurality of pins to form a pinout in response to a first design, a second design and an attribute and (B) determining one or more placement constraints, one or more groups of the pins, and routing of the pins in response to the attribute.
The objects, features and advantages of the present invention include providing a method and/or architecture for automatic placement of bus I/O pins that may (i) simplify PCB routing, (ii) optimize timing, (iii) minimize trace crossovers and vias, (iv) reduce design time and cost, (v) improve design reliability, and/or (vi) automatically overcome architectural constraints.


REFERENCES:
patent: 5128871 (1992-07-01), Schmitz
patent: 5983277 (1999-11-01), Heile et al.
PCI Local Bus Specification, Revision 2.2, Dec. 18

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