Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-07-17
2007-07-17
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
10917693
ABSTRACT:
Presented herein is a system and method for byte slice based DDR timing closure. In one embodiment, there is presented a method for synthesizing/laying out a dual data rate memory, said method comprising synthesizing/laying out a portion of the dual data rate memory; replicating the portion; and placing the synthesized/laid out portion and the replicated portions in proximity to a corresponding plurality of pads.
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D'Luna Lionel
Hughes Tom
Radhakrishnan Sathish Kumar
Broadcom Corporation
Kik Phallaka
McAndrews Held & Malloy Ltd.
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