Boundary-scan cells with improved timing characteristics

Details Boundary-scan cells with improved timing characteristics Boundary-scan cells with improved timing characteristics

1998-09-15

2001-07-24

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06266801

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to integrated circuits and more particularly concerns boundary-scan cell designs with improved timing characteristics.
2. Description of the Related Art
Electronic systems typically have one or more printed circuit boards (PCB's) and one or more integrated circuit (IC) chips. IC chips typically include input/output pins (I/O pins) that are commonly coupled to interconnects of a PCB. Testing the performance of electronic systems, which include PCB's and IC chips typically require testing at chip level, at board level, and at system level. Testing at board level includes testing interconnects of the PCB. Testing at system level includes analysis of interconnections between IC chips, PCB's, and other devices.
In order to enhance the testability at board-level and system-level, a common design practice at chip-level now consists of incorporating IEEE Standard 1149.1 logic, or JTAG (Joint Test Action Group). In order to build JTAG logic, boundary-scan (BS) cells are inserted for all I/Os and control (enable) signals Q for tri-state outputs in chip design. As a simplistic illustration,
FIG. 1A
shows a partial circuit design
10
including a core
12
that communicates with input/output logic to establish a path to a pin
18
. The core can therefore communicate data to a tri-state output buffer
14
, and also communicate data into the core
12
via an input buffer
16
.
FIG. 1B
shows a partial circuit design
10
′ after boundary scan (BS) cells have been inserted to convert the circuit design into a JTAG testable circuit. In this example, three types of boundary scan (BS) cells
20
,
22
, and
24
are used to accomplish control, output, and input, respectively.
FIG. 1C
provides a more detailed logic level diagram of the control BS cell
20
. The control BS cell
20
includes a multiplexer (mux m1)
26
, a flip flop
28
, a latch
30
, and a multiplexer (mux m2)
32
. In this design, the multiplexer
32
functions as the mode control logic. Therefore, when Mode=0, the core
12
will be able to communicate with the I/O pad
18
, and therefore establish the functional path. Alternatively, when Mode=1, the JTAG path will be established to enable boundary scan testing (under JTAG mode).
FIG. 1D
illustrates another example in which the core
12
communicates to input/output circuitry (in a multiple bit case) that includes tri-state output buffers
14
and input buffers
16
. In this example, the signal coming from the core
12
is shown to be an enable signal (enable_net) that provides the control signals
34
to the various tri-state output buffers
14
in the circuit design. When the core
12
is designed in a particular integrated circuit device, the designer takes into consideration the amount of drive strength required to drive the enable control signal
34
, depending upon the number of tri-state output buffers leading to input/output pads
18
.
FIG. 1E
illustrates the insertion of a control BS cell
20
into the design of FIG.
1
D. In this example, the enable signal
34
is now only communicated to the single load of the multiplexer (mux m2)
32
, as opposed to delivering the enable signal
34
to each load of the tri-state output buffers
14
. A critical drawback of this design is that the drive strength designed into the core logic
12
was initially set to drive a plurality of tri-state output buffers
14
as shown in
FIG. 1D
, not a single multiplexer.
Consequently, the output drive strength provided by the enable signal
34
to the multiplexer
32
will produce a severe overdriving. As is well known, severe consequences such as, greater heat dissipation, greater power consumption, and greater current will necessarily result from this overdriving. In some cases, the multiplexer
32
may be overdriven so much that it will become damaged and therefore jeopardize the functionality of the chip in both the functional mode and in the test mode. Another disadvantage of having too much drive strength delivered to the multiplexer
32
is that the core
12
was initially designed with more logic to drive the plurality of tri-state output buffers
14
, and now the silicon area used for that extra drive strength will, in essence, be wasted. As a result, the design and fabrications costs of the IC will be much greater than required.
Although the core logic can be redesigned to reduce the drive strength when JTAG testability is needed, such laborious redesign is generally not recommended. This is because the logic designer has already optimized the core logic
12
in terms of timing to meet the desired IC specification. When the core logic is subsequently modified to reduce the driving strength provided to the multiplexer
32
, the timing parameters optimized for the entire integrated circuit design may become offset. Of course, such redesign can be performed while at the same time modifying the timing parameters of the integrated circuit device, but such redesign may be very time consuming, and therefore, greatly increase the cost of the IC due to the incorporation of basic JTAG logic.
Even though the multiplexer
32
is provided with a larger drive strength than necessary after the insertion of the control BS cell
20
in
FIG. 1E
, the multiplexer
32
on its own is a very weak driver. Consequently, the drive strength provided by the multiplexer
32
to each of the tri-state output buffers
14
may be weaker than is actually required. One technique used to increase the drive strength of the signal provided from the output of the multiplexer
32
is to include an additional buffer
37
just before driving the tri-state output buffers
14
.
Although this achieves the desired greater drive strength, the introduction of the output buffer
37
will have the disadvantage of introducing a “gate delay” and “write delay” that are in addition to the “one-mux” delay produced by the multiplexer
32
. Although only 4 input/output pads
18
are shown in
FIG. 1E
, in designs where the multi-bit count is high, a larger degree of buffering will be needed in order to provide the signal output by the multiplexer
32
with sufficient drive strength. Accordingly, as more buffering is needed at the output of the multiplexer
32
, more timing alterations will be introduced. Of course, anytime the delays are introduced along the functional path (identified herein by darker signal paths), the more likely it will be that the IC will no longer function under its proper timing specification.
Accordingly, although adding boundary scan cells to achieve testability is highly desirable, the insertion of boundary scan cells into IC designs introduces substantial disadvantages in terms of the aforementioned overdriving problems and timing problems. These problems may therefore prevent the integrated circuit device from properly operating at a desired frequency in functional mode (also known as system mode).
In view of the foregoing, there is a need for boundary scan circuitry that can be easily incorporated into integrated circuit designs without impacting upon the circuits' timing characteristics. Additionally, there is a need for boundary scan circuitry that can be inserted into existing designs while at the same time, providing the designer incorporating the boundary scan cells with a predictable level of load on Q during functional mode operation.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing new and improved integrated circuit boundary scan cells that substantially eliminate timing problems and overdriving problems in single and multiple bit applications. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several inventive embodiments of the present invention are described below.
In one embodiment, an integrated circuit design incorporating boundary scan cells having improved timing characteristics is disclosed. The design in

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