Buffering technique using structured delay skewing

Details Buffering technique using structured delay skewing Buffering technique using structured delay skewing

2008-07-22

2008-07-22

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07404162

ABSTRACT:
A line buffering technique in which a plurality of line buffers are arranged based on a determined average number of branches and stages that are necessary to implement the buffers based on design constraints. In an exemplary embodiment, the line buffers may be arranged in any buffer topology arrangement meeting the average number of branches and the number of stages design constraints.

REFERENCES:
patent: 7073145 (2006-07-01), Fry et al.

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