Bottom-up approach for synthesis of register transfer level...

Details Bottom-up approach for synthesis of register transfer level... Bottom-up approach for synthesis of register transfer level...

2006-03-07

2006-03-07

Thompson, A. M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C076S002000, C076S003000, C076S004000, C076S005600

Reexamination Certificate

active

07010774

ABSTRACT:
A method for synthesizing a register transfer level (RTL) based design employs a bottom-up approach to generate a final top-level design. The top-level design is divided into a plurality of sub-modules. Each of the sub-modules is then independently synthesized using an RTL based design approach and independently adapted to conform to timing requirements produced for each of the sub-modules using time budgets that are based on the top-level timing requirements. Once the sub-modules are synthesized and pass individual timing requirements specific for those sub-modules, the sub-modules are integrated to form a top-level design. The top-level design may then be verified for timing requirements and other formal requirements.

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