Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-04-05
2004-07-20
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06766499
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to electronic design, and more particularly to computer aided electronic design tools. Even more particularly, the present invention relates to computer aided design with buffer insertion functionality.
Electronic design automation (EDA) tools, or computer aided design (CAD) tools are used by designers of electronic circuits to create representations of circuit configurations, including representations of electronic cells (e.g., transistors), and interconnects between them. Because commercially available electronic design automation (EDA) tools allow designers to construct circuit layouts and simulate the performance of the circuit using a computer, without requiring the costly and lengthy process of fabrication and design, these electronic design automation tools are very useful.
Modern electronic circuits are often designed to perform tasks very quickly; thus must be designed so that signals traveling within the circuits are timed properly to successfully perform the tasks. A problem faced by designers is signal transmission delay throughout the electronic circuit caused by the electronic cells and the interconnects between them. Recent and continuing technical advances in the art of circuit fabrication, allowing the construction of sub-micron electronic cells, has decreased the delay introduced by the electronic cells (cell delays) and thus has increased the delay in signal transmission introduced by the interconnects (interconnect delays), due primarily to resistance and capacitance, relative to the cell delays. As a result, the interconnect delays often exceed the cell delays.
To reduce ramp delays caused by the resistance and capacitance of the interconnect(a form of interconnect delay), buffer cells are inserted within the interconnect. The buffer cells themselves, however, introduce gate delays into the interconnect, and therefore, there exists a tradeoff between reducing ramp delays and minimizing gate delays. For a given application, there exists a number of buffer cells (in part dependent on the type of buffer cell) that represents a balance between the ramp delay and the gate delays in an interconnect structure that meets both signal propagation and timing constraints.
One method of establishing this number of buffer cells, when there is only one receiving cell, involves inserting buffer cells based solely upon the length of the interconnect. This method however, only roughly approximates the number of buffer cells because parameters of the driving electronic cell (driving cell), and the signal output of the driving cell, are not utilized in connection with the parameters of the interconnect, such as capacitance, resistance, and inductance.
Another method includes laying out the interconnects between electronic cells and then inserting buffer cells based upon the designer's best estimation. The method then involves performing a computer implemented analysis, such as using a SPICE analysis, that calculates the signal propagation delay and/or attenuation for that design based upon the actual parameters of the driving cell, buffer cells and interconnect. The designer then adjusts the number, location, and/or type of the buffer cells in hopes of improving the signal propagation delay and/or attenuation, and again performs a computer implemented analysis to determine if a more optimal number, placement and/or type of buffer cell can be found. This approach may require many iterations before an optimal number, placement and type of buffer cells is determined. Further, each iteration is often time consuming because the calculations are done real time. Therefore, this iterative or “trial and error” approach, while more accurate than the previously discussed “pure length” approach, is too time consuming for practical use if a desired number, placement and type of buffer cells is to be determined.
There exists, therefore, a need for a system and method that are able to quickly and accurately determine, for a particular interconnect, the types and number of buffers to maintain signal speed within tolerance, and reduce uncertainly in signal propagation to ensure signal timing constraints are met. The present invention advantageously addresses the needs above as well as other needs.
SUMMARY OF THE INVENTION
The present invention advantageously addresses the needs above as well as other needs by providing a computer aided design system for buffer insertion.
In one embodiment, the invention can be characterized as a computer readable medium encoded with instructions for executing the steps of: receiving information about a driving cell from a layout tool, receiving information about an interconnect from a layout tool, determining buffer cell information based upon information about the driving cell and the interconnect by accessing a previously defined library lookup table, relaying the buffer cell information from the library look up table to the layout tool.
In another embodiment, the invention can be characterized as a method comprising the steps of: generating a library lookup table, receiving information about a driving cell and an interconnect from a layout tool, determining buffer cell information by accessing the library lookup table, relaying the buffer cell information from the library look up table to the layout tool.
In a further embodiment, the invention can be characterized as a buffer insertion system comprising: a library lookup table, receiving means for obtaining information about a driving cell and an interconnect from a layout tool, buffer determination means for obtaining at least one type of buffer cell, a quantity of buffer cells, and a distance between buffer cells from the library lookup table based upon a net length and the information about the driving cell, sending means for delivering the at least one type of buffer cell, the quantity of buffer cells, and the distance between buffer cells to the layout tool.
In an additional embodiment, the invention can be characterized as a buffer insertion system comprising: a memory, the memory storing electronic design automation (EDA) software, an interconnect data set, and a driving cell data set, wherein each of the interconnect data set and the driving cell data set have multiple data fields for storing data values; a database, the database storing a library lookup table with predetermined data relating the driving cell data set and the interconnect data set to predetermined buffer cell information; a CPU connected to the memory, the CPU providing the predetermined buffer cell information-to the Electronic Design Automation software wherein the providing includes: receiving a predetermined buffer cell information request from the EDA software, the interconnect data set, and the driving cell data set; selecting a predetermined buffer cell information from the database; sending the predetermined buffer cell information to the memory.
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Graef Stefan
Lahner Juergen
Mbouombouo Benjamin
Fitch Even Tabin & Flannery
Kik Phallaka
LSI Logic Corporation
Smith Matthew
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