Buffer insertion with adaptive blockage avoidance

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06898774

ABSTRACT:
A method, computer program product, and data processing system for inserting buffers into integrated circuit routing trees are disclosed. The present invention dynamically modifies a Steiner tree configuration as needed to derive a maximal slack solution that takes into account blockages such as those presented by IP blocks.

REFERENCES:
patent: 5629860 (1997-05-01), Jones et al.
patent: 6044209 (2000-03-01), Alpert et al.
patent: 6401234 (2002-06-01), Alpert et al.
patent: 6467069 (2002-10-01), Mehrotra et al.
patent: 6519745 (2003-02-01), Srinivas et al.
patent: 6557145 (2003-04-01), Boyle et al.
patent: 6591411 (2003-07-01), Alpert et al.
patent: 6615401 (2003-09-01), Gasanov et al.
patent: 6622291 (2003-09-01), Ginetti
patent: 20030212976 (2003-11-01), Drumm
Hrkic et al., “S-Tree: a technique for buffered routing tree synthesis”, Jun. 10-14, 2002 Design Automation Conference, 2002. Proceedings. 39th , pp.: 578-583.*
Alpert et al., “Steiner tree optimization for buffers. Blockages and bays”, May 6-9, 2001 Circuits and Systems, 2001. ISCAS 2001. The 2001 International Symposium on , vol.: 5 , pp.: 399-402 vol. 5.*
Alpert et al., “Wire Segmenting for Improved buffer insertion”, Jun. 9-13, 1997, Design Automation Conference, 1997. Proceedings of the 34th, pp.: 588-593.*
Zhou et al., “Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Location”, IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems, vol. 19, No. 7, Jul. 2000, pp. 819-824.
Van Ginneken, “Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay”, International Business Machines Corporation, Abstract, pp. 865-868.
Gupta et al., “The Elmore Delay as a Bound for RC Trees with Generalized Input Signals”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, No. 1, Jan. 1997, pp. 95-104.
Alpert et al., “Buffer Insertion with Accurate Gate and Interconnect Delay Computation”, International Business Machines Corporation, Abstract, pp. 479-484.
Alpert et al., “Wire Segmenting for Improved Buffer Insertion”, IBM Austin Research Laboratory, Austin, Texas, Abstract, Abstract, pp. 588-593.
Alpert et al., “Steiner Tree Optimization for Buffers, Blockages, and Bays”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, No. 4, Apr. 2001, pp. 556-562.
Cong et al., “Buffer Block Planning for Interconnect-Driven Floorplanning”, Department of Computer Science, University of California, Los Angeles, CA, Abstract, pp. 358-363.
Alpert et al., “Buffer Insertion for Noise and Delay Optimization”, International Business Machines Corporation, Abstract, pp. 362-367.
Cong et al., “Routing Tree Construction Under Fixed Buffer Locations”, ACM Digital Library, 2000, pp. 379-384.
Tang et al., “A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing Under Obstacle Constraints”, University of Texas at Austin, Austin, TX, IEEE, 2001, pp. 49-56.
Lai et al., “Maze Routing with Buffer Insertion and Wiresizing”, ACM Digital Library, 2000, pp. 374-378.
Jagannathan et al., “A Fast Algorithm for Context-Aware Buffer Insertion”, ACM Digital Library, 2000, pp. 368-373.
Lillis et al., “Simultaneous Routing and Buffer Insertion for High Performance Interconnect”, University of California, San Diego, La Jolla, CA, IEEE 1996, pp. 148-153.
Alpert et al., “Buffered Steiner Trees for Difficult Instances”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, No. 1, Jan. 2002, pp. 3-13.
Cormen et al., “Interval Trees”, Introduction to Algorithms, MIT Press, 2001, pp. 311-316.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Buffer insertion with adaptive blockage avoidance does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Buffer insertion with adaptive blockage avoidance, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Buffer insertion with adaptive blockage avoidance will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3383214

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.