Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-10-11
2010-11-02
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07827513
ABSTRACT:
A method for identifying and modifying, in a VLSI hierarchical chip design, parent buffer placements which lead to wiring track inefficiencies with respect to data flow and the parent placement area geometry. Parent placement area is reviewed and a subset is categorized and distinguished as either horizontal slots or vertical slots. Buffer to buffer data flow is reviewed for cases where data flow direction is either strongly horizontal or strongly vertical. Situations where buffer to buffer data flow is oriented in the same direction as the parent placement slots in which the buffers reside are reported. Additionally, an attempt is made to find a valid placement location for the buffers excluding parent placement areas oriented in the same direction as the data flow.
REFERENCES:
patent: 6622291 (2003-09-01), Ginetti
patent: 6662349 (2003-12-01), Morgan
patent: 6826740 (2004-11-01), Drumm
patent: 7036103 (2006-04-01), Miller
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patent: 2002/0184607 (2002-12-01), Alpert
patent: 2003/0163795 (2003-08-01), Morgan et al.
Berry Christopher J.
Jalkowski Adam R.
Palumbo Joseph J.
Augspurger Lynn L
International Business Machines - Corporation
Kinnaman, Jr. William A.
Whitmore Stacy A
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