Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-06-15
2003-12-02
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06658632
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to high performance integrated circuits (“ICs”) and, more particularly, to boundary scan cells implemented at output and bi-directional pins of ICs, without impacting the performance of the ICs, to facilitate testing of the ICs and their interconnections on printed circuit boards.
2. The Background Art
As is known to those skilled in the art, boundary scan is a collection of design rules applied to an integrated circuit (“IC”) that enables testing and debugging at the IC level, at the printed circuit board level, and at the module or system level. The design rules for Boundary Scan are imposed by IEEE/ANSI Standard IEEE 1149.1-1990, which is accepted throughout the industry. The IEEE 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture define the functionality and design guidelines for boundary scan cells. Within these guidelines, IC designers are free to implement the boundary scan logic and circuits in accordance with the design requirements and objectives of each particular IC.
FIG. 1
is a high-level block diagram illustrating an exemplary IC
100
incorporating Boundary Scan testing capabilities in accordance with the IEEE-1149-1990 standard. As shown in
FIG. 1
, IC
100
includes a plurality of input pins
105
, a plurality of output pins
110
, and application logic section
120
. I/O pins may be substituted for any of pins
105
,
110
and three-state pins may be substituted for-output pins
110
, but these are omitted in
FIG. 2
for clarity. Any number of input and/or output pins
105
and/or
110
may be included in IC
100
.
Still referring to
FIG. 1
, for the purposes of Boundary Scan testing, circuitry necessary to implement normal IC functionality is deemed to reside within application logic section
120
. In other words, application logic section
120
performs the normal (i.e., non-boundary scan testing) functions performed by IC
100
. Naturally, the precise configuration or nature of application logic
120
varies according to the requirements of each IC.
Boundary Scan Cells (“BSCs”)
200
selectively couple and isolate application logic section
120
from input pins
105
and output pins
110
. Typically, each BSC
200
that is used with an input pin
105
couples between an input pin
105
and application logic
120
. Similarly, each BSC
200
that is used with an output pin
110
couples between application logic
120
and an output pin
110
. Not all of the pins of IC
100
are required to be associated with a BSC
200
. For example, power pins and pins providing bus request signals may omit an association with a BSC
200
.
Each BSC
200
receives a common MODE input signal. In addition, each BSC
200
couples to other BSCs
200
in a serial manner, such that all of the BSCs
200
collectively form Boundary Scan Register
140
. A test data input (“TDI”) input pin
130
drives the input of Boundary Scan Register
140
. The last BSC
200
in Boundary Scan Register
140
couples to a test data output (“TDO”) output pin
150
. A boundary scan chain (not shown) is formed from series connections between all Boundary Scan Registers
140
of the ICs included on a printed circuit board.
As described so far, BSCs
200
and application logic
120
represent conventional BSCs and application logic sections. Furthermore, in accordance with the IEEE 1149.1-1990 standard, IC
100
includes a test access port (“TAP”) controller
155
, a state decoder (not shown in FIG.
1
), instruction register
165
, and instruction register decoder
170
similar or identical to those known in the art. As is also known in the art, IC
100
may include other data registers
175
, such as an Identification (“ID”) register (which uses an IC identification code), bypass register, and the like.
Instruction register
165
and other registers
175
couple in parallel across the input and output of Boundary Scan Register
140
. Registers
165
and
175
represent shift registers receiving input data from TDI pin
130
and supplying output data through TDO pin
150
. Parallel outputs from instruction register
165
couple to inputs of instruction register decoder
170
. Thus, instruction register decoder
170
determines which Boundary Scan testing instruction is currently active for IC
100
, and which data register is to be selected to be connected between TDI and TDO (and thus controls the select inputs of multiplexer
160
shown in FIG.
1
).
The Test Mode Select (“TMS”) and Test Clock (“TCK”) signals are applied at TMS and TCK pins
180
and
185
, respectively. Pins
180
and
185
couple to TAP controller
155
and couple in parallel among the various ICs
100
included in a board-level or higher-level system (not shown). As is known in the art, the TMS and TCK signals are typically generated by an external Boundary Scan master (not shown). TAP controller
155
represents a state machine sequencing between various states in response to the TMS signal logic level when clocked by the TCK signal, and produces various signals (to be described in more detail below) depending on the states and state transitions executed by TAP controller
155
. The IEEE 1149.1-1990 test bus uses both clock edges of TCK. TMS and TDI are sampled on the rising edge of TCK, while TDO changes on the falling edge of TCK.
The state of the TMS signal presenting at pin
180
when clocked by the TCK signal controls the sequencing of TAP controller
155
through its various states. These states and their transitions are defined in the IEEE- 1149.1-1990 standard, and well-known to those of ordinary skill in the art. They are not discussed in further detail herein so as not to overcomplicate the present description. For more, information, the official IEEE-1149.1-1990 standard may be consulted. Specific TAP controller
155
states and their corresponding output signals are -discussed throughout this document where appropriate.
The TAP is controlled by the Test Clock (“TCK”) and Test Mode Select (“TMS”) inputs. These two inputs determine the TAP controller state transitions, which in turn determine whether an Instruction Register scan or Data Register scan is performed. The TAP controller is driven by the TCK input, and responds to the TMS input in accordance to a state diagram that is well known to those skilled in the art.
FIG. 2
is a block diagram illustrating mode selection logic
190
operating in conjunction with two BSCs, specifically illustrating one BSC
200
associated with an input pin
105
and one BSC
200
associated with an output pin
110
. For a given BSC
200
, one data input of multiplexer (“MUX”)
204
may receive a system signal via input pin
105
(in the case of an input BSC) or application logic
120
(in the case of an output BSC). The other data input of multiplexer
204
may receive serial data from a previous BSC, or from TDI pin
130
(in the case of the first BSC in an IC). The selection input of MUX
204
may be driven by a signal from the state decoder (not shown in
FIG. 1
) indicating that TAP controller
155
(from
FIG. 1
) is operating in the Shift-DR state, as is known to those skilled in the art. Polarities may be arranged such that serial data from the direction of TDI pin
130
is presented at the output of multiplexer
204
during the Shift-DR state, whereas the system signal is presented at the output of multiplexer
204
during all other states.
The output of multiplexer
204
may drive a data input of capture flip-flop (“CAP FF.”)
206
. As is known to those skilled in the art, capture flip-flop
206
may receive a clock signal with timing equivalent to the TCK signal
185
(from
FIG. 1
) when TAP controller
155
(from
FIG. 1
) is operating in the data register (DR) states, and is clocked by the Clock-DR signal. While shifting data through a boundary scan chain, capture flip-flop
206
connects in a serial chain and serves as part of Boundary Scan Register
140
(FIG.
1
).
The output of capture flip-flop
206
couples to a data input of an update flip-flop (“UPD FF”)
208
Narayanan Sridhar
Parulkar Ishwardutt
Ritchie David B.
Smith Matthew
Thelen Reid & Priest LLP
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