Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-09-04
2004-04-20
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06725442
ABSTRACT:
BACKGROUND
1. Field of Invention
The invention relates generally to integrated circuits having repeated configurable logic and configurable interconnect structures provided therein. The invention relates more specifically to the problem of thoroughly and quickly testing large numbers and different types of interconnect resources such as those provided within an integrated circuit monolith that contains a programmable logic circuit such as a field programmable gate array (FPGA).
2. Description of Related Art
As the density of programmably-reconfigurable, digital logic circuitry within integrated circuits (IC's) increases, and as the signal-processing speed of such logic also increases, the ability of all parts of the interconnect within the IC to correctly and consistently route all signals in timely and accurate fashion between spaced-apart logic sections (e.g., CLB's or Configurable Logic Blocks) becomes more and more important to proper operation of the integrated circuit.
Individual ones of mass-produced, in-field re-programmable IC's may have a number of localized defects within their interconnect resources such as: regional or spot short-circuits; broken-open lines; lines stuck-at a particular logic level; stuck-open signal routers; and stuck-closed signal routers. Any one or more of these and yet other circuit defects can interfere with proper device operation. Accordingly it is desirable to be able to test the interconnect resources of such mass-produced IC's thoroughly, or as near thoroughly as practical, in order to provide a commensurate level of confidence (e.g., close to 100% test coverage) regarding the in-field operability of the interconnect. It is further desirable to be able to test the interconnect resources of such mass-produced IC's in a time efficient manner and to minimize the use of expensive test equipment thereby allowing for economical verification of the hypothesis that all or a substantial portion of the IC's resources are functioning as intended.
Testing of interconnect resources (hereafter, interconnect verification testing or ‘IVT’) at high speed and with thorough; or close-to-thorough coverage, is particularly difficult to achieve in cases where the interconnect is programmably re-configurable and the IVT is being conducted after the IC chips have been packaged in their respectively insulating, and pin-out limited carriers (e.g., ceramic IC packages). One reason for the difficulty is that each part of the configurable interconnect can have a large number of connection permutations, all of which may need to be tested during IVT in order to provide confidence that the configurable interconnect is fully operational. Another reason for the difficulty is that direct access to all internal nodes of the IC is usually no longer available after the IC has been encased in its package. Testers are limited to electrically coupling to the chip's interior by way of the limited number of external pins or terminals that are provided by the package's pinout.
Even before the above-described post-packaging phase, in a so-called, wafer-sort testing phase which occurs prior to packaging, the number of on-die, exposed nodes available to the testing equipment is limited by a number of factors including the number and types of probe fingers on the test equipment and the number of probe-able nodes (e.g., pads) provided on each IC die. While these constraints on testability are applicable to most IC's, they are particularly a problem for FPGA's.
More specifically, when it comes to re-programmable logic arrays such as Field Programmable Gate Arrays (FPGA's), practitioners in the art of mass-production testing have begun to recognize that very large numbers of conductors of differing lengths, of differing orientations, and of other differing attributes may have to be each individually and methodically tested even as such conductors are connected to respective, but operationally-questionable, programmable signal routers (e.g., PIP's—Programmable Interconnect Points) of various kinds. Practitioners want to be able to economically test each interconnect line for its ability to cleanly transmit a logic “1” level or pulse without interference from surrounding lines or routers, and counterposingly, to be able to economically and further test each interconnect line for its ability to cleanly transmit a logic “0” level or pulse, again without interference from surrounding lines or routers. This can be a massive undertaking in densely wired circuitry such as modern FPGA's because their signal-routing switchboxes (e.g., PIP matrices) tend to be heavily populated and this leads to exponentially increasing numbers of possible interconnect permutations.
One approach that has been proposed for tackling this massive problem is called AND/OR tree testing. It is described in a research paper by W. K. Huang, F. J. Meyer, and F. Lombardi, entitled “An Approach for Detecting Multiple Faults in FPGAs”, Dept. of Computer Science, Texas A&M University). Briefly, when AND/OR tree testing is carried out, selected ones of the programmable logic circuits of the FPGA are configured to each implement a four-input, receipt-verifying and result-forwarding circuit consisting of: (1) an AND gate, (2) an OR gate, and (3) a 2-to-1 dynamic multiplexer.
More specifically, under AND/OR tree testing, the progression of a respective logic “1” pulse can be timed and verified as it snakes its way from a first I/O pin, and through a logic-blocks implemented series of AND gates to a second I/O pin. If the logic “1” pulse (a 0-to-1-to-0 transition) is detected at the second I/O pin, that information can be used to verify that interconnect resources within the series chain of AND gates can propagate such a logic “1” pulse. Similarly, the progression of a respective logic “0” pulse can be timed and verified as it snakes its way from the same first I/O pin, and through a logic-blocks implemented series of OR gates to the second I/O pin. If the “0” pulse is seen to be faithfully reproduced a short time later at the second I/O pin, that information can be used to verify that interconnect resources within the series chain of OR gates can propagate such a “0” pulse.
The reason why the four-input, receipt-verifying and result-forwarding circuit is used in the AND/OR tree testing of W. K. Huang et. al is to avoid having to re-program the under-test FPGA in between the “1” pulse propagating test and the “0” pulse propagating test. Each re-programming of a given FPGA can consume as much as 500 mS (milliseconds) or more. It is the re-programming rather than the testing itself which tends to consume the bulk of overall test time. With Huang's dynamically-switchable, receipt-verifying and result-forwarding circuit, one or the other of a combinatorial logic series of AND gates or OR gates may be established for timing and verifying respective propagation of a “1” pulse and a “0” pulse.
A main drawback of the AND/OR tree method is that a very large number of different FPGA configuration patterns may still have to be programmed into a same IC in order to verify that all, or a fair majority of its interconnect resources are working properly. As already explained, each re-programming of a new configuration pattern into the FPGA can consume as much as 500 mS (milliseconds) or more. If the number of different patterns needed for high-confidence verification is on the order of 500 or more, then a single, under-test IC may consume as much as 250 seconds (over 4 minutes) of testing time or more, simply for the pattern programming time. This magnitude of per-chip testing time is not acceptable. Note that we are not even counting the amount of additional time it may take to actually perform the interconnect verification tests, or other logic function tests. The pattern re-programming time is by itself a major problem.
For one specific family of high-density FPGA's (60,000 gate devices), the present inventors calculated that approximately 800 pattern re-programmings wo
Cote Richard T.
Nguyen Brenda
Pham Xuan D.
Sharpe-Geisler Bradley A.
Garbowski Leigh M.
Lattice Semiconductor Corporation
Lin Sun James
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