Scan design for double-edge-triggered flip-flops

Details Scan design for double-edge-triggered flip-flops Scan design for double-edge-triggered flip-flops

2005-08-30

2005-08-30

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06938225

ABSTRACT:
A double-edge-triggered flip-flop scan cell. The double-edge-triggered flip-flop scan cell provides the capability to capture and output data for each edge of a clock signal in a functional mode of a host integrated circuit. In a test mode, the double-edge triggered flip-flop scan cell enables test data to be scanned into and out of the scan cell to provide observability and controllability of the scan cell internal state.

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1 Low power design using double edge triggered flip-flops Hossain, R.; Wronski, L.D.; Albicki, A. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.: 2, Issue: 2 , Jun. 1994, pp.: 261-265.
2 Double edge triggered devices: Speed and power constraints Hossain, R.; Wronski, L.; Albicki, A. Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on May 1993, pp.: 1491-1494, vol. 3.

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