Scalable scan-path test point insertion technique

Details Scalable scan-path test point insertion technique Scalable scan-path test point insertion technique

2006-10-31

2006-10-31

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07131081

ABSTRACT:
A logic circuit comprising at least one input, one output and a delay fault circuit. The delay fault circuit includes a first standard scan cell, a combinational test point positioned immediately after the first standard scan cell in a scan chain and a second standard scan cell positioned immediately after the combinational test point in the scan chain.

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